Integrated circuits are extensively tested both during and after production and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as dynamic random access memories ("DRAMs"), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power up routine when power is initially applied to the computer system. DRAMs are generally tested by writing known data to each location in the memory and then reading data from each memory location to determine if the read data matches the written data. As the capacity of DRAMs and other memory devices continues to increase, the time required to write and then read data from all memory locations continues to increase, even though memory access times continue to decrease.
Various proposals have been made to decrease the time required to test memory devices, such as DRAMs. The time required to write known data to memory devices has been reduced by such approaches as simultaneously writing the same data to each column of each array in the memory device one row at a time. However, some types of testing require that the word lines be kept at a fixed positive voltage for an extended period of time, such as tens of milliseconds. When there are thousands of word lines in one memory device, this testing takes long periods of time since only one word line in each bank of the memory device may be accessed at a time.
Other approaches for reducing testing time include internal circuitry for transferring data from each column of one row to the next row without requiring the memory to be addressed. These approaches have reduced the time required to write known data or a known pattern of data to the memory array. However, when the initial or "seed" row to which data are written is defective, this approach to speeding of testing fails.
Additionally, it is very difficult to assess some error margins. In testing one type of error margin, known as "writeback margin", it is difficult to measure slew rates at which circuitry involved in writing new data to memory cells limits a maximum clock frequency at which the memory device may continue to operate reliably. Since several different portions of the memory device may limit the maximum clock frequency, a series of simple "go-no go" tests at increasing clock frequencies will not provide insight into which mechanism is limiting the maximum clock frequency.
A new memory device design may be empirically found to be susceptible to certain defects, that are most readily and efficiently identified through testing using one or more combinations of rows that could, not be anticipated when the memory device was designed. Accordingly, only having a capability to invoke tests using combinations of rows chosen from a limited number of pre-programmed combinations is less than optimal.
In the prior art approaches to writing the same data to multiple rows, the rows are often activated at the same time. As a result, large currents are induced in the memory device, sometimes causing signals to be coupled into unintended memory locations and providing the appearance of memory device failure when the memory device may be capable of normal operation.
There is therefore a need to be able to write data to a memory device, while reducing testing time and increasing testing flexibility, that can be implemented on integrated circuits having memory arrays.